module test #(parameter TMP = 10'd100)
(
    input clk,
    input rst_n,
    input [10:0]data,
    output reg res
);

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        res <= 1'b0;
    end
    else begin
        res <= (data > TMP);
    end
end

endmodule
